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19-1171; Rev 0; 12/96
Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface
__________________General Description
The +5V MAX5250 combines four low-power, voltageoutput, 10-bit digital-to-analog converters (DACs) and four precision output amplifiers in a space-saving, 20pin package. In addition to the four voltage outputs, each amplifier's negative input is also available to the user. This facilitates specific gain configurations, remote sensing, and high output drive capacity, making the MAX5250 ideal for industrial-process-control applications. Other features include software shutdown, hardware shutdown lockout, an active-low reset that clears all registers and DACs to zero, a user-programmable logic output, and a serial-data output. Each DAC has a double-buffered input organized as an input register followed by a DAC register. A 16-bit serial word loads data into each input/DAC register. The 3-wire serial interface is compatible with SPITM/QSPITM and MicrowireTM. It allows the input and DAC registers to be updated independently or simultaneously with a single software command. All logic inputs are TTL/CMOSlogic compatible.
______________________________Features
o Four 10-Bit DACs with Configurable Output Amplifiers o +5V Single-Supply Operation o Low Supply Current: 0.85mA Normal Operation 10A Shutdown Mode o Available in 20-Pin SSOP and DIP Packages o Power-On Reset Clears all Registers and DACs to Zero o SPI/QSPI and Microwire Compatible o Simultaneous or Independent Control of DACs via 3-Wire Serial Interface o User-Programmable Digital Output o Schmitt-Trigger Inputs for Direct Optocoupler Interface o 12-Bit Upgrade Available: MAX525
MAX5250
_________________Ordering Information
PART TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 SSOP INL (LSB) 1/2 1 1/2 1
________________________Applications
Digital Offset and Gain Adjustment Microprocessor-Controlled Systems Industrial Process Controls Automatic Test Equipment Remote Industrial Controls Motion Control
MAX5250ACPP MAX5250BCPP MAX5250ACAP MAX5250BCAP
Ordering Information continued on last page. Pin Configuration appears at end of data sheet.
_________________________________________________________________________Functional Diagram
DOUT CL PDL DECODE CONTROL INPUT REGISTER A DGND AGND VDD REFAB FBA
MAX5250
DAC REGISTER A OUTA DAC A FBB OUTB DAC B FBC OUTC DAC C FBD OUTD DAC D
16-BIT SHIFT REGISTER
INPUT REGISTER B
DAC REGISTER B
INPUT REGISTER C
DAC REGISTER C
SR CONTROL CS DIN SCLK
LOGIC OUTPUT UPO
INPUT REGISTER D
DAC REGISTER D
REFCD
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface MAX5250
ABSOLUTE MAXIMUM RATINGS
VDD to AGND............................................................-0.3V to +6V VDD to DGND ...........................................................-0.3V to +6V AGND to DGND ..................................................................0.3V REFAB, REFCD to AGND ...........................-0.3V to (VDD + 0.3V) OUT_, FB_ to AGND...................................-0.3V to (VDD + 0.3V) Digital Inputs to DGND.............................................-0.3V to +6V DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V) Continuous Current into Any Pin.......................................20mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 8.00mW/C above +70C) .................640mW SSOP (derate 8.00mW/C above +70C) ......................640mW CERDIP (derate 11.11mW/C above +70C) .................889mW Operating Temperature Ranges MAX5250_C_P ......................................................0C to +70C MAX5250_E_P ...................................................-40C to +85C MAX5250BMJP ................................................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V 10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. Output buffer connected in unity-gain configuration (Figure 9).) PARAMETER Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity Offset Error Offset-Error Tempco Gain Error (Note 1) Gain-Error Tempco Power-Supply Rejection Ratio REFERENCE INPUT Reference Input Range Reference Input Resistance Reference -3dB Bandwidth Reference Feedthrough Signal-to-Noise Plus Distortion Ratio SINAD VREF RREF Code dependent, minimum at code 554 hex VREF = 0.67Vp-p Input code = all 0s, VREF = 3.6Vp-p at 1kHz VREF = 1Vp-p at 25kHz, code = full scale 0 10 650 -84 72 VDD - 1.4 V k kHz dB dB PSRR 4.5V VDD 5.5V GE 1 100 800 SYMBOL N INL DNL VOS 6 1.0 MAX5250A MAX5250B Guaranteed monotonic CONDITIONS MIN 10 0.25 0.5 1.0 1.0 6.0 TYP MAX UNITS Bits LSB LSB mV ppm/C LSB ppm/C V/V
STATIC PERFORMANCE--ANALOG SECTION
MULTIPLYING-MODE PERFORMANCE
2
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Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. Output buffer connected in unity-gain configuration (Figure 9).) PARAMETER DIGITAL INPUTS Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing Current into FB_ OUT_ Leakage Current in Shutdown Start-Up Time Exiting Shutdown Mode Digital Feedthrough Digital Crosstalk POWER SUPPLIES Supply Voltage Supply Current Supply Current in Shutdown Reference Current in Shutdown VDD IDD (Note 3) (Note 3) 4.5 0.85 10 0.01 5.5 0.98 20 1 V mA A A CS = VDD, DIN = 100kHz RL = SR To 1/2LSB, VSTEP = 2.5V Rail-to-rail (Note 2) 0.6 10 0 to VDD 0 0.01 15 5 5 0.1 1 V/s s V A A s nV-s nV-s VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 0.5 0.13 0.4 V V VIH VIL IIN CIN VIN = 0V or VDD 0.01 8 2.4 0.8 1.0 V V A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5250
Note 1: Guaranteed from code 3 to code 1023 in unity-gain configuration. Note 2: Accuracy is better than 1LSB for VOUT = 6mV to VDD - 60mV, guaranteed by a power-supply rejection test at the end points. Note 3: RL = , digital inputs at DGND or VDD.
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Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface MAX5250
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. Output buffer connected in unity-gain configuration (Figure 9).) PARAMETER SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Raise to CS Rise Hold Time DIN Setup Time DIN Hold Time SCLK Rise to DOUT Valid Propagation Delay SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold Time CS Pulse Width High SYMBOL tCP tCH tCL tCSS tCSH tDS tDH tD01 tD02 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 40 40 100 CONDITIONS MIN 100 40 40 40 0 40 0 80 80 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns TIMING CHARACTERISTICS (Figure 6)
__________________________________________Typical Operating Characteristics
(VDD = +5V, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE
MAX5250-01
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
REFAB SWEPT 0.67Vp-p RL = 5k CL = 100pF
MAX5250-02
SUPPLY CURRENT vs. TEMPERATURE
950 900 SUPPLY CURRENT (A) 850 800 750 700 650 600 550 CODE = FFC hex
MAX5250-03
0.075 0.050 0.025 0 INL (LSB) -0.025 -0.050 -0.075 -0.100 -0.125 0.4 RL = 5k 1.2 2.0 2.8 3.6 REFERENCE VOLTAGE (V)
0
1000
-4 RELATIVE OUTPUT (dB)
-8
-12
-16
-20 4.4 0 500k 1.0M 1.5M 2.0M FREQUENCY (Hz) 2.5M 3.0M
500 -55 -40 -20
0
20
40
60
80 100 120
TEMPERATURE (C)
4
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Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface
____________________________Typical Operating Characteristics (continued)
(VDD = +5V, TA = +25C, unless otherwise noted.)
MAX5250
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5250-04
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX5250-05
OUTPUT FFT PLOT
VREF = 1kHz, 0.006V TO 3.6V RL = 5k CL = 100pF
MAX5250-10
1000 950 SUPPLY CURRENT (A) 900 850 800 750 700 650 600 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 CODE = FFC hex
0.50 0.45 0.40 THD + NOISE (%) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 DAC CODE = FULL SCALE REFAB = 1Vp-p RL = 5k CL = 100pF
0
SIGNAL AMPLITUDE (dB) 100
-20
-40
-60
-80
5.6
1
10 FREQUENCY (kHz)
-100 0.5
1.6
2.7
3.8
4.9
6.0
SUPPLY VOLTAGE (V)
FREQUENCY (kHz)
FULL-SCALE ERROR vs. LOAD
MAX5250-09
REFERENCE FEEDTHROUGH AT 1kHz
REFAB INPUT SIGNAL SIGNAL AMPLITUDE (dB) -20 VREF = 3.6Vp-p @ 1kHz RL = 5k CL = 100pF
MAX5250-11
0
0
FULL-SCALE ERROR (LSB)
-0.25
-0.50
-40
-0.75
-60 OUTA FEEDTHROUGH
-1.00
-80
-1.25 0.01 0.1 1 LOAD (k) 10 100
-100 0.5
1.2
1.9
2.6
3.3
4.0
FREQUENCY (kHz)
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Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface MAX5250
____________________________Typical Operating Characteristics (continued)
(VDD = +5V, VREF = 2.5V, RL = 5k, CL = 100pF, TA = +25C, unless otherwise noted.)
MAJOR-CARRY TRANSITION
MAX5250-07
DIGITAL FEEDTHROUGH (SCLK = 100kHz)
MAX5250-08
CS 5V/div
SCLK, 2V/div
OUTB, AC COUPLED 100mV/div
OUTA, AC COUPLED 10mV/div
10s/div
2s/div CS = PDL = CL = 5V, DIN = 0V DAC A CODE SET TO 800 hex
ANALOG CROSSTALK
MAX5250-12
DYNAMIC RESPONSE
MAX5250-13
OUTA, 1V/div GND OUTB, AC COUPLED 10mV/div
OUTA, 1V/div
10s/div DAC A CODE SWITCHING FROM 00C hex TO FFC hex DAC B CODE SET TO 800 hex
10s/div SWITCHING FROM CODE 000 hex TO FB4 hex OUTPUT AMPLIFIER GAIN = +2
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Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME AGND FBA OUTA OUTB FBB REFAB CL CS DIN SCLK DGND DOUT UPO PDL REFCD FBC OUTC OUTD FBD VDD Analog Ground DAC A Output Amplifier Feedback DAC A Output Voltage DAC B Output Voltage DAC B Output Amplifier Feedback Reference Voltage Input for DAC A and DAC B Clear All DACs and Registers. Resets all outputs (OUT_, UPO, DOUT) to 0, active low. Chip-Select Input. Active low. Serial-Data Input Serial-Clock Input Digital Ground Serial-Data Output User-Programmable Logic Output Power-Down Lockout. Active low. Locks out software shutdown if low. Reference Voltage Input for DAC C and DAC D DAC C Output Amplifier Feedback DAC C Output Voltage DAC D Output Voltage DAC D Output Amplifier Feedback Positive Power Supply FUNCTION
MAX5250
_______________________________________________________________________________________
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Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface
FB_
R
R
R
OUT_
2R
2R S0
2R S1
2R D0
2R D9
REF_ AGND
SHOWN FOR ALL 1s ON DAC
Figure 1. Simplified DAC Circuit Diagram
_______________Detailed Description
The MAX5250 contains four 10-bit, voltage-output digital-to-analog converters (DACs) that are easily addressed using a simple 3-wire serial interface. It includes a 16-bit data-in/data-out shift register, and each DAC has a doubled-buffered input composed of an input register and a DAC register (see Functional Diagram). In addition to the four voltage outputs, each amplifier's negative input is available to the user. The DACs are inverted R-2R ladder networks that convert a digital input (10 data bits plus 2 sub-bits) into equivalent analog output voltages in proportion to the applied reference voltage inputs. DACs A and B share the REFAB reference input, while DACs C and D share the REFCD reference input. The two reference inputs allow different full-scale output voltage ranges for each pair of DACs. Figure 1 shows a simplified circuit diagram of one of the four DACs.
The impedance at each reference input is code dependent, ranging from a low value of 10k when both DACs connected to the reference have an input code of 554 hex, to a high value exceeding several giga ohms (leakage currents) with an input code of 000 hex. Because the input impedance at the reference pins is code dependent, load regulation of the reference source is important. The REFAB and REFCD reference inputs have a 10k guaranteed minimum input impedance. When the two reference inputs are driven from the same source, the effective minimum impedance is 5k. A voltage reference with a load regulation of 6ppm/mA, such as the MAX873, would typically deviate by 0.006LSB (0.015LSB worst case) when driving both MAX5250 reference inputs simultaneously at 2.5V. Driving the REFAB and REFCD pins separately improves reference accuracy. In shutdown mode, the MAX5250's REFAB and REFCD inputs enter a high-impedance state with a typical input leakage current of 0.01A. The reference input capacitance is also code dependent and typically ranges from 20pF with an input code of all 0s to 100pF at full scale.
MAX5250
Output Amplifiers
All MAX5250 DAC outputs are internally buffered by precision amplifiers with a typical slew rate of 0.6V/s. Access to each output amplifier's inverting input provides the user greater flexibility in output gain setting/ signal conditioning (see the Applications Information section). With a full-scale transition at the MAX5250 output, the typical settling time to 1/2LSB is 10s when loaded with 5k in parallel with 100pF (loads less than 2k degrade performance). The MAX5250 output amplifier's output dynamic responses and settling performances are shown in the Typical Operating Characteristics.
Power-Down Mode
The MAX5250 features a software-programmable shutdown that reduces supply current to a typical value of 10A. The power-down lockout pin (PDL) must be high to enable shutdown mode. Writing 1100XXXXXXXXXXXX as the input-control word puts the MAX5250 in power-down mode (Table 1).
Reference Inputs
The two reference inputs accept positive DC and AC signals. The voltage at each reference input sets the full-scale output voltage for its two corresponding DACs. The reference input voltage range is 0V to (VDD - 1.4V). The output voltages (VOUT_) are represented by a digitally programmable voltage source as: VOUT_ = (VREF x NB / 1024) x Gain where NB is the numeric value of the DAC's binary input code (0 to 1023), VREF is the reference voltage, and Gain is the externally set voltage gain.
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Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface
In power-down mode, the MAX5250 output amplifiers and the reference inputs enter a high-impedance state. The serial interface remains active. Data in the input registers is retained in power-down, allowing the MAX5250 to recall the output states prior to entering shutdown. Start up from power-down either by recalling the previous configuration or by updating the DACs with new data. When powering up the device or bringing it out of shutdown, allow 15s for the outputs to stabilize.
MAX5250
SCLK
SK
DIN
SO
MAX5250
DOUT*
SI*
MICROWIRE PORT
Serial-Interface Configurations
The MAX5250's 3-wire serial interface is compatible with both MicrowireTM (Figure 2) and SPITM/QSPITM (Figure 3). The serial input word consists of two address bits and two control bits followed by 10+2 data bits (MSB first), as shown in Figure 4. The 4-bit address/ control code determines the MAX5250's response outlined in Table 1. The connection between DOUT and the serial-interface port is not necessary, but may be used for data echo. Data held in the MAX5250's shift register can be shifted out of DOUT and returned to the microprocessor (P) for data verification. The MAX5250's digital inputs are double buffered. Depending on the command issued through the serial interface, the input register(s) can be loaded without affecting the DAC register(s), the DAC register(s) can be loaded directly, or all four DAC registers can be updated simultaneously from the input registers (Table 1).
CS
I/O
*THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5250, BUT MAY BE USED FOR READBACK PURPOSES.
Figure 2. Connections for Microwire
+5V
DOUT*
MISO*
SS
DIN
MOSI
MAX5250
SCLK
SCK
Serial-Interface Description
The MAX5250 requires 16 bits of serial data. Table 1 lists the serial-interface programming commands. For certain commands, the 10+2 data bits are "don't cares." Data is sent MSB first and can be sent in two 8-bit packets or one 16-bit word (CS must remain low until 16 bits are transferred). The serial data is composed of two DAC address bits (A1, A0) and two control bits (C1, C0), followed by the 10+2 data bits D9...D0, S1, S0 (Figure 4). Set both sub-bits (S1, S0) to zero. The 4-bit address/control code determines: * The register(s) to be updated * The clock edge on which data is to be clocked out via the serial-data output (DOUT) * The state of the user-programmable logic output (UPO) * If the part is to go into shutdown mode (assuming PDL is high) * How the part is configured when coming out of shutdown mode.
CS I/O
SPI/QSPI PORT
CPOL = 0, CPHA = 0 *THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5250, BUT MAY BE USED FOR READBACK PURPOSES.
Figure 3. Connections for SPI/QSPI
MSB ..................................................................................LSB 16 Bits of Serial Data Address Bits A1 A0 Control Bits C1 C0 Data Bits MSB ..................................LSB D9 .....................................D0, S1, S0 10+2 Data Bits
4 Address/ Control Bits
Figure 4. Serial-Data Format
_______________________________________________________________________________________ 9
Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface MAX5250
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD A1 0 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 A0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 C1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 C0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D9.................D0 MSB.............LSB 10-bit DAC data 10-bit DAC data 10-bit DAC data 10-bit DAC data 10-bit DAC data 10-bit DAC data 10-bit DAC data 10-bit DAC data XXXXXXXXXX 10-bit DAC data XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX S1 0 0 0 0 0 0 0 0 X 0 X X X X X X S0 0 0 0 0 0 0 0 0 X 0 X X X X X X FUNCTION
Load input register A; DAC registers unchanged. Load input register B; DAC registers unchanged. Load input register C; DAC registers unchanged. Load input register D; DAC registers unchanged. Load input register A; all DAC registers updated. Load input register B; all DAC registers updated. Load input register C; all DAC registers updated. Load input register D; all DAC registers updated. Update all DAC registers from their respective input registers (also exit shutdown mode). Load all DAC registers from shift register (also exit shutdown mode). Enter shutdown mode (provided PDL = 1). UPO goes low (default). UPO goes high. No operation (NOP) to DAC registers Mode 1, DOUT clocked out on SCLK's rising edge. All DAC registers updated. Mode 0, DOUT clocked out on SCLK's falling edge. All DAC registers updated (default).
"X" = Don't care
Figure 5 shows the serial-interface timing requirements. The chip-select pin (CS) must be low to enable the DAC's serial interface. When CS is high, the interface control circuitry is disabled. CS must go low at least tCSS before the rising serial clock (SCLK) edge to properly clock in the first bit. When CS is low, data is clocked into the internal shift register via the serial-data input pin (DIN) on SCLK's rising edge. The maximum guaranteed clock frequency is 10MHz. Data is latched into the appropriate MAX5250 input/DAC registers on CS's rising edge. The programming command Load-All-DACs-From-ShiftRegister allows all input and DAC registers to be simultaneously loaded with the same digital code from the input shift register. The no operation (NOP) command leaves the register contents unaffected and is useful when the MAX5250 is configured in a daisy chain (see the Daisy Chaining Devices section). The command to
change the clock edge on which serial data is shifted out of DOUT also loads data from all input registers to their respective DAC registers.
Serial-Data Output (DOUT)
The serial-data output, DOUT, is the internal shift register's output. The MAX5250 can be programmed so that data is clocked out of DOUT on SCLK's rising edge (Mode 1) or falling edge (Mode 0). In Mode 0, output data at DOUT lags input data at DIN by 16.5 clock cycles, maintaining compatibility with Microwire, SPI/QSPI, and other serial interfaces. In Mode 1, output data lags input data by 16 clock cycles. On power-up, DOUT defaults to Mode 0 timing.
User-Programmable Logic Output (UPO)
The user-programmable logic output, UPO, allows an external device to be controlled via the MAX5250 serial interface (Table 1).
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Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface MAX5250
CS COMMAND EXECUTED 1 DIN DOUT (MODE 0) A1 A0 C1 C0 D9 D8 D7 8 D6 D5 9 D4 D3 D2 D1 D0 S1 16 S0
SCLK
DATA PACKET (N) A1 A0 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 A1
MSB FROM PREVIOUS WRITE DATA PACKET (N-1) DOUT (MODE 1) A1 A0 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 DATA PACKET (N) A1
MSB FROM PREVIOUS WRITE DATA PACKET (N-1) DATA PACKET (N)
Figure 5. Serial-Interface Timing Diagram
CS tCSO SCLK tDS DIN tDO1 DOUT tDO2 tDH tCSS tCL tCH tCP tCSH tCS1
tCSW
Figure 6. Detailed Serial-Interface Timing Diagram
Power-Down (PDL)
The power-down lockout pin PDL disables software shutdown when low. When in shutdown, transitioning PDL from high to low wakes up the part with the output set to the state prior to shutdown. PDL can also be used to wake up the device asynchronously.
Daisy Chaining Devices
Any number of MAX5250s can be daisy chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain (Figure 7).
Since the MAX5250's DOUT pin has an internal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive load. Refer to the serial-data-out VOH and VOL specifications in the Electrical Characteristics. Figure 8 shows an alternate method of connecting several MAX5250s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC.
11
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Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface MAX5250
MAX5250
SCLK DIN CS SCLK DIN CS DOUT DIN CS
MAX5250
SCLK DOUT DIN CS
MAX5250
SCLK DOUT
TO OTHER SERIAL DEVICES
Figure 7. Daisy-Chaining MAX5250s
DIN SCLK CS1 CS2 CS3 TO OTHER SERIAL DEVICES
CS
CS
CS
MAX5250
SCLK DIN SCLK DIN
MAX5250
SCLK DIN
MAX5250
Figure 8. Multiple MAX5250s Sharing a Common DIN Line
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Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface
__________Applications Information
Unipolar Output
For a unipolar output, the output voltages and the reference inputs have the same polarity. Figure 9 shows the MAX5250 unipolar output circuit, which is also the typical operating circuit. Table 2 lists the unipolar output codes. For rail-to-rail outputs, see Figure 10. This circuit shows the MAX5250 with the output amplifiers configured with a closed-loop gain of +2 to provide 0V to 5V full-scale range when a 2.5V reference is used.
Bipolar Output
The MAX5250 outputs can be configured for bipolar operation using Figure 11's circuit: VOUT = VREF [(2NB / 1024) - 1] where NB is the numeric value of the DAC's binary input code. Table 3 shows digital codes (offset binary) and corresponding output voltages for Figure 11's circuit.
+5V VDD
MAX5250
REFERENCE INPUTS
MAX5250
REFAB DAC A REFCD FBA
Table 2. Unipolar Code Table
DAC CONTENTS MSB LSB 1111 1111 11(00) ANALOG OUTPUT 1023 +VREF ( ------ ) 1024 513 +VREF ( ------ ) 1024 512 +VREF +VREF ( ------ )= -------- 1024 2 511 +VREF ( ------ ) 1024
OUTA FBB DAC B OUTB FBC
1000
0000
01(00)
1000
0000
00(00)
DAC C OUTC FBD DAC D
0111
1111
11(00)
0000 0000
0000 0000
01(00) 00(00)
1 +VREF ( ------ ) 1024 0V
OUTD AGND DGND
Table 3. Bipolar Code Table
DAC CONTENTS MSB LSB 1111 1000 1000 0111 0000 0000 ( ) Sub-bits 1111 0000 0000 1111 0000 0000 11(00) 01(00) 00(00) 11(00) 01(00) 00(00) ANALOG OUTPUT 511 +VREF ( ------ ) 512 1 +VREF ( ------ ) 512 0V 1 -VREF ( ------ ) 512 511 -VREF ( ------ ) 512 512 -VREF ( ------ )= -VREF 512
Figure 9. Unipolar Output Circuit
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Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface MAX5250
Using an AC Reference
REFERENCE INPUTS +5V VDD FBA 10k 10k DAC A OUTA FBB 10k 10k DAC B OUTB FBC 10k 10k DAC C OUTC FBD 10k 10k DAC D OUTD AGND DGND
MAX5250
REFAB REFCD
In applications where the reference has AC signal components, the MAX5250 has multiplying capability within the reference input range specifications. Figure 12 shows a technique for applying a sine-wave signal to the reference input where the AC signal is offset before being applied to REFAB/REFCD. The reference voltage must never be more negative than DGND. The MAX5250's total harmonic distortion plus noise (THD + N) is typically less than -72dB (full-scale code), given a 1Vp-p signal swing and input frequencies up to 25kHz. The typical -3dB frequency is 650kHz, as shown in the Typical Operating Characteristics graphs.
Digitally Programmable Current Source
The circuit of Figure 13 places an NPN transistor (2N3904 or similar) within the op-amp feedback loop to implement a digitally programmable, unidirectional current source. This circuit can be used to drive 4-20mA current loops, which are commonly used in industrialcontrol applications. The output current is calculated with the following equation: IOUT = (VREF / R) x (NB / 1024) where NB is the numeric value of the DAC's binary input code and R is the sense resistor shown in Figure 13.
VREFAB = VREFCD = 2.5V
Figure 10. Unipolar Rail-to-Rail Output Circuit
+5V R1 REF_ +5V FB_ VOUT DAC OUT_ -5V DAC_ OUT_ 500mVp-p 10k REF_ VDD R2 AC REFERENCE INPUT 26k
1/2 MAX492
MAX5250
R1 = R2 = 10k 0.1%
MAX5250
AGND DGND
Figure 11. Bipolar Output Circuit
14
Figure 12. AC Reference Input Circuit
______________________________________________________________________________________
Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface
__________________Pin Configuration
REF_ VL
MAX5250
MAX5250
DAC_ OUT_ IOUT
TOP VIEW
AGND 1 2N3904 FBA 2 OUTA 3 OUTB 4 R FBB 5 REFAB 6 CL 7 CS 8
20 VDD 19 FBD 18 OUTD 17 OUTC
FB_
MAX5250
16 FBC 15 REFCD 14 PDL 13 UPO 12 DOUT 11 DGND
Figure 13. Digitally Programmable Current Source
DIN 9 SCLK 10
Power-Supply Considerations
On power-up, all input and DAC registers are cleared (set to zero code) and DOUT is in Mode 0 (serial data is shifted out of DOUT on the clock's falling edge). For rated MAX5250 performance, limit REFAB/REFCD to less than 1.4V below VDD. Bypass VDD with a 4.7F capacitor in parallel with a 0.1F capacitor to AGND. Use short lead lengths and place the bypass capacitors as close to the supply pins as possible.
DIP/SSOP
Grounding and Layout Considerations
Digital or AC transient signals between AGND and DGND can create noise at the analog outputs. Tie AGND and DGND together at the DAC, then tie this point to the highest-quality ground available. Good printed circuit board ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines. Wire-wrapped boards are not recommended.
______________________________________________________________________________________
15
Low-Power, Quad, 10-Bit Voltage-Output DAC with Serial Interface MAX5250
_Ordering Information (continued)
PART MAX5250AEPP MAX5250BEPP MAX5250AEAP MAX5250BEAP MAX5250BMJP TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 SSOP 20 CERDIP* INL (LSB) 1/2 1 1/2 1 1
___________________Chip Information
TRANSISTOR COUNT: 4337
*Contact factory for availability and processing to MIL-STD-883.
________________________________________________________Package Information
DIM A A1 B C D E e H L INCHES MILLIMETERS MIN MAX MIN MAX 0.068 0.078 1.73 1.99 0.002 0.008 0.05 0.21 0.010 0.015 0.25 0.38 0.004 0.008 0.09 0.20 SEE VARIATIONS 0.205 0.209 5.20 5.38 0.0256 BSC 0.65 BSC 0.301 0.311 7.65 7.90 0.025 0.037 0.63 0.95 0 8 0 8 INCHES MILLIMETERS MAX MIN MAX MIN 6.33 0.239 0.249 6.07 6.33 0.239 0.249 6.07 7.33 0.278 0.289 7.07 8.33 0.317 0.328 8.07 0.397 0.407 10.07 10.33
21-0056A
E
H
C
L
DIM PINS
e
A B D
A1
SSOP SHRINK SMALL-OUTLINE PACKAGE
D D D D D
14 16 20 24 28
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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